A memory cell comprising first and second storage circuits for storing first and second logic levels includes (FIGS. 1a, 1b) two storage points A and B, and two access transistors T7 and T8 of an appropriate type. Such a memory cell may be of the SRAM type. Each access transistor connects a storage point of the cell to an associated row of words WL or /WL (complementary to WL), and to storage means or circuits MS1, MS2 connected back-to-front relative to each other. The storage points A, B store complementary logic levels.
In the example of FIG. 1a, the storage circuits MS1, MS2 of the memory cell, also known as latches, are two inverters connected back-to-front relative to each other between the storage points A, B. Each inverter is formed by two different types of transistors series-connected between a power supply terminal VDD of the inverter, and ground GND of the circuit. The common drain of the transistors forms the output of the inverter, and the common gate of the transistors form the input of the inverter.
In the example of FIG. 1b, the storage circuits MS1, MS2 of the memory cell each comprise two transistors connected back-to-front relative to each other. The first storage circuit MS1 includes transistors T11, T12. The second storage circuit MS2 includes transistors T21, T22. From an electrical viewpoint, behavior of the memory cells of FIGS. 1a and 1b are the same. The cells differ simply by the connection of the transistors T12 and T22.
To program a logic 1 in the cell of FIG. 1b, an active access signal WL is applied to the gates of the transistors T7 and T8, and complementary potentials are applied to the sources of the transistors T7 and T8. For example, VDD may be applied to the source of T7, and GND may be applied to the source of T8.
During the programming of a logic 1, the second storage circuit MS1 is active. The transistors T21, T22 are on, and the potential VDD (corresponding to the logic 1) appears at output S2, and the potential GND appears at input E2 (corresponding to a logic 0).
On the contrary, the first storage circuit MS2 is passive. The transistors T11, T12 are off. The potential VDD at the input E1 is dictated by the potential at the output S2, and the potential GND at the output S1 is dictated by the potential at the input E2. Naturally, to program a logic 0, an active access signal WL is applied to the gates of the transistors T7, T8, and inverse complementary potentials are applied to the sources of the transistors T7, T8. GND may be applied to the source of T7, and VDD may be applied to the source of T8. Behavior of the first and second storage circuits are inverted relative to the case where a logic 1 is programmed.
To read the content of the cell of FIG. 1b, the active access signal WL is simply applied to the gates of the transistors T7, T8, and the potentials at the sources of the transistors T7, T8 are measured.
The memory cells are highly sensitive to the logic random events (or soft errors), i.e., the loss of information at the storage point where one of the two logic levels is stored. This may be caused by an addition of energy that comes from external the memory cell and is not wanted.
The logic random events or soft errors may have different origins. A logic random event is caused, for example, by the impact of an energy particle, for example a heavy ion, at a storage point of the circuit. Such a logic random event is known as a Single Event Upset (SEU). A logic random event can also be induced by one-time capacitive coupling between two layers of a same integrated circuit. The term frequently used in this case is glitch or single event transient (SET).
Electronic circuits are increasingly sensitive to logic random events, and when there is a reduction in the size of their components. Thus, for circuits made with technologies of 0.25 μm or less, the logic random events are far too frequent to be overlooked.
Inasmuch as the trend is towards the use of ever smaller technologies, and especially technologies smaller than 0.25 μm, the problems of sensitivity of the electronic circuits now commonly appear in the field of computer hardware as well as in a variety of fields such as transportation, avionics, medical equipment, etc.
The impact of an energy particle or the capacitive coupling of two layers gives rise to a contribution of charge in the circuit which generally results in a current spike and a voltage spike on a digital or analog signal, at a point of a circuit. This may be for example, the point of impact in the case of a SEU, a coupling point in the case of a glitch, etc. The voltage variation is generally very brief, typically on the order of a few picoseconds to a few hundreds of picoseconds.
The voltage variation, however, may have a very high amplitude in a SRAM cell. The storage point of the SRAM cell behaves like a capacitor that charges the electron/hole pairs created during the impact of the energy particle or during the capacitive coupling of two layers. If C denotes the value of the capacitance and ΔQ denotes the variation in charge of the capacitance resulting from the contribution of external charges, this results in a variation in voltage ΔV at the terminals of the capacitance such that ΔV=ΔQ/C.
Current technologies enable the making of circuits whose dimensions are ever smaller. The capacitance C of the storage points may then attain very low values so that, even for a small quantity of charges ΔQ, the voltage variation ΔV may reach a high level. A major variation in voltage may cause the logic level, stored in the storage point that undergoes the voltage variation, to switch over. The switch-over of a logic level then causes the switch-over of the complementary logic level. Since the complementary logic levels confirm each other, the memory cell is in a stable state different from the initial state.
For example, after the programming of a logic 1 in the cell of FIG. 1b, the potential at the point A is equal to VDD and the potential at the point B is equal to GND. The second storage circuit is active. If a logic random event, for example, disturbs the gate of the transistor T22, the potential VDD is immediately restored at the gate by the transistor T21 which is on.
The first storage circuit, on the contrary, is passive. If a random error disturbs, for example, the gate of the transistor T12, the transistor T11 which is inactive is not able to restore the potential GND at the gate of T12. T12 comes on and the potential GND appears at the drain of T11 (with the switch-over of the first storage circuit) as well as at the gate of T22 which goes off. The gate of T12 and the drain of T11 then impose the potential VDD on the gate of T11 and the drain of T22 (switch-over of the second storage circuit). The memory cell has thus changed states.
To address this problem, U.S. Pat. Nos. 6,147,899 and 5,570,313 propose the making of double cells comprising two single cells (as shown in FIG. 1a or 1b) connected back-to-front relative to each other so that, if the content of the single cell is disturbed by a random event, the other cell restores the content of the disturbed single cell.
These approaches, however, are not satisfactory. Indeed, they display assymmetrical sensitivity depending on the storage point which receives external charges. Also, they may be difficult to implement in an integrated circuit since they imply two bulky cells which are difficult to bring close together, links between the two cells that are lengthy and difficult to position between the components of these two cells, and sensitivity which although reduced remains high, etc.